Special Hardware

• SMP/OpenMP
  • SMP Tagged Code Objects
    • Parallel Loop == smp_for
  • SMP Code Objects and Code Generator
    • Thread ID
    • Barrier
    • SMP Codegenerator
  • OpenMP Unparser
    • Parallel For
    • Parallel Region
• SIMD
  • Targeting SIMD Vector Instructions
    • Simple Example: Intel AVX 4-way Double Precision
    • Stepwise Code Generation
    • Complex Vectorization Example
  • Tags
    • Real Vectorization
    • Complex Vectorization
  • Vectorization Rules
    • Simple Vectorization Rule Example
    • Formula Rewrite
  • Wrapping
    • VWrap Transformation
    • VWrap in Context of Search
  • Special Role of Stride Permutations
    • TL: Lift Stride Permutation to Non-Terminal Level
    • TL in Context of Search
  • Architecture Specific Permutations
    • Looking up vectorized Implementations for TL
    • SIMD ISA Database and Bootstrapping a Vector Architecture
  • ISA Database and Hashed Breakdowns
    • Generic Breakdown Rules to Look Up Architecture Specific Code
  • Stride Permutatiopn Identities as Rules
    • Generic Breakdown Rules to Look Up Architecture Specific Code
  • SPL And Σ-SPL Vector Objects
    • Generate The Example
    • Inspecting the Vector Objects
  • Vector SPL Objects
    • Vector Tensor SPL Object
  • Vector Σ-SPL Objects
    • Vector Gather
  • Vector RC Objects: Manage Data Layout
    • Vector RC Class
    • VRC, VRCL, VRCR, VRCLR
    • Terminate VRC, VRCL, VRCR, VRCLR
  • Vector SumsGen and Rewriting
    • Default Sumsgen Handles Vector SPL to Σ-SPL
    • Rewrite Rule Strategies
    • Compile Strategies
  • Vector CodeGen
  • Vector Instructions
  • Vector Strength Reduction and Fixup Rules
  • Vector Unparser
  • ISA Definition
  • Vector Benchmarking Infrastructure