Highly-Efficient FFT Core in HLS

What is it?

We open-source a parameterized FFT core implementation in Vivado HLS.

Overview

The practical use of High-level Synthesis (HLS) for FPGAs may compromise resource efficiency, which is a common design goal in FPGA programming. Specifically, when designing the iterative datapath for computing a FFT, combining naive HLS code with compiler optimizations can fail to saturate the BRAM ports and incur significant penalty in clock frequency. To solve this problem, we suggest that the target datapath should be made explicit in HLS code. Using this solution, our FFT cores reduce the FFT latency by N cycles for the radix-2 N-point FFT comparing with previous HLS-based work and the Xilinx LogiCORE FFT. Meanwhile, our designs achieve comparable peak frequency and consume similar resources to Xilinx.

Benchmarks

Compared to the Xilinx LogiCORE FFT IP, our implementations achieve slightly better latency with comparable resource utilization and peak frequency.

HLS Code Download

The HLS code for FFT is available here under non-viral license (BSD-style license). For further reading, you can also download an extended abstract regarding this topic.

References

1. G. Xu, et al.
   Optimizing FFT Resource Efficiency of FPGA using High-level Synthesis
   IEEE High Performance Extreme Computing Conference (HPEC), 2017

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More Information

Contact: Guanglin Xu, guanglix (at) xxxandrew.cmu.edu (delete xxx)