SPIRAL Hardware

On this page we overview hardware design generators that we developed in this project and make available to the public. In each case you have to click on the link to be forwarded to the particular site.

DFT (Discrete Fourier Transform) Verilog IP Generator

We provide web interface access to our generator for customized DFT hardware. A simple web form allows the user to specify parameters that control tradeoffs between area and speed. From the parameters, the Verilog code is generated and can be downloaded and used under the included license. Go to the DFT website.

Multiplierless Constant Multiplication

We have developed algorithms and tools that generated multiplier blocks that multiply by one or several constants "multiplierless," that is, using only additions, subtractions, and shifts. Go to the multiplierless website.

Sorting Network Verilog IP Generator

We provide web interface access to our generator for customized sorting hardware. A simple web form allows the user to specify parameters that control tradeoffs between area and speed. From the parameters, the Verilog code is generated and can be downloaded and used under the included license. Go to the sorting network website.

Multiplierless FIR/IIR Filters

We provide a web interface to our generator for multiplierless finite impulse response (FIR) and infinite impulse response (IIR) filters.

Structured LDPC Codes

We develop FPGA implementation of a class of structured LDPC codes and analyze these codes. Go to the LDPC site.

Multi-gigabit optical OFDM

We are developing the first optical OFDM transceiver operating at 10 Gbit/s using real-time DSP.

Highly-Efficient FFT Core in HLS

We open-source a parameterized FFT core implementation in Vivado HLS. Go to the FFT HLS site.