DFT IP Generator

Explanation

The SPIRAL DFT IP Generator is a fast generator for customized Discrete Fourier Transform (DFT) soft IP cores. The user has control over a variety of parameters that control the functionality of the generated core as well as parameters that control resource tradeoffs such as area and throughput. Below the input form, the resource usage is dynamically estimated and displayed. For more information, please see the references below.

The web-based generator seen here is an early (2005) prototype, described in [7]. The resource estimation component (see [6]) targets a Xilinx Virtex-II Pro FPGA, synthesized under Xilinx ISE 7.1.03i.

Our ongoing work extends upon this greatly and produces considerably higher-quality designs over a much wider design space. For more information, please see our other references below (in particular, our 2008 DAC paper [3]). If you have an interesting application that could benefit from our newer generator, please feel free to contact us at the address given at the bottom of this page.

Generator

Input: parameters controlling DFT size, data width, twiddle width, data ordering, scaling mode, parallelism p, twiddle storage method, FIFO threshold

Output: synthesizable Verilog for an n-point DFT with parallelism p

Benchmarks

Here are a few example benchmarks of the latest iteration of our generator, which is an improvement and considerable extension of the one above (see [1,2,3,4,5]). All designs are synthesized using Xilinx ISE, and all cost and performance data are collected after place/route.

DFT 1024, fixed point, throughput and latency:

DFT 256, floating point, throughput:

2-D DFT 256 x 256, fixed point, throughput:

FPGA accelerated software on the FPGA's embedded PowerPC processor. Both software and hardware are generated (see [4]):

References

Markus Püschel, Peter A. Milder, and James C. Hoe
Permuting Streaming Data Using RAMs
to appear in Journal of the ACM, 2009
submitted for patent application
Peter A. Milder, James C. Hoe, and Markus Püschel
Automatic Generation of Streaming Datapaths for Arbitrary Fixed Permutations
to appear in Design, Automation and Test in Europe (DATE), 2009
Peter A. Milder, Franz Franchetti, James C. Hoe and Markus Püschel
Formal Datapath Representation and Manipulation for Implementing DSP Transforms
Proc. Design Automation Conference (DAC), 2008
Paolo D'Alberto, Franz Franchetti, Peter A. Milder, Aliaksei Sandryhaila, James C. Hoe, Jeremy Johnson, José M. F. Moura, Markus Püschel
Generating FPGA-Accelerated DFT Libraries
Proc. IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) 2007
Peter A. Milder, Franz Franchetti, James C. Hoe and Markus Püschel
Discrete Fourier Transform Compiler: From Mathematical Representation to Efficient Hardware
CSSI Technical Report #CSSI-07-01, Carnegie Mellon University, 2007
Peter A. Milder, Mohammad Ahmad, James C. Hoe and Markus Püschel
Fast and Accurate Resource Estimation of Automatically Generated Custom DFT IP Cores
Proc. FPGA, pp. 211-220, 2006
Grace Nordin, Peter A. Milder, James C. Hoe and Markus Püschel
Automatic Generation of Customized Discrete Fourier Transform IPs
Proc. Design Automation Conference (DAC), pp. 471-474, 2005

More publications on IP cores for FPGAs/ASICs

More publications on the discrete/fast Fourier transform

Online software generator for the discrete/fast Fourier transform

More information

Contact: Peter Milder: pam [AT-SIGN] ece [DOT] cmu [DOT] edu